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  • The 15th (2015) Yamazaki-Teiichi Prize Winner Semiconductor & Semiconductor Device

The 15th (2015) Yamazaki-Teiichi Prize Winner Semiconductor & Semiconductor Device

Development of Impact Assessment Technologies for Terrestrial Neutron-Induced Soft-Errors in Semiconductor Devices and Pr

Winner Winner
Hidefumi Ibe
Mar. 1975 Graduated, Faculty of Science, Kyoto University
Apr. 1975 Joined Nuclear Power Research Center, Hitachi, Ltd.
Aug. 1997 Transferred to Production Technology Research Center, Hitachi, Ltd.
Jun. 2011 Compulsory retirement, Still working as continuing employee
Winner Winner
Tadanobu Toba
Apr. 1983 Joined Production Technology Research Center, Hitachi, Ltd.
Oct. 2006 Principal Researcher, Production Technology Research Center
Mar. 2013 Completed Professional Degree Course (System Safety), Graduate School of Management of Technology, Nagaoka University of Technology
Apr. 2015 Affiliation changed to new name due to reorganization of research center
Winner Winner
Kenichi Shinbo
Apr. 1993 Joined Production Technology Research Center, Hitachi, Ltd.
Apr. 1997 Entered Research Course in Electronic Engineering of Hitachi Keihin Senior Technical School (Tokyo University)
Apr. 1998 Returned to Production Technology Research Center, Hitachi, Ltd.
Apr. 2015 Affiliation changed to new name due to reorganization of research center

Reason for award

In the latter half of the 1990s, it became apparent that soft errors (temporary malfunctions) of semiconductor memory occur due to environmental neutrons which rain down onto the earth’s surface from space. The recipients showed that soft errors in SRAM (high-speed semiconductor memory) will become more severe in the future, and elucidated the mechanism of soft errors by developing a high-precision simulator for neutron-induced soft errors in SRAM. In anticipation of broader effects due to soft errors, they devised circuits enabling reliable detection and correction, successfully developed a high-reliability 130-nm 8-Mb SRAM, and contributed to the shipment of products with a value of 18 billion yen annually since 2001. They developed technology for evaluating soft errors using a semi-monochromatic neutron irradiation test method, and achieved international standardization of the technology in 2006. In addition, they determined that intermittent failures with routers (communication devices which link up networks) that surfaced in 2009 are due to neutron-induced soft errors in built-in FPGA (semiconductor integrated circuits whose logical functions can be programmed by the user). They successfully developed an FPGA built-in diagnosis circuit, which autonomously performs high-speed detection and correction of soft errors, and thereby realized a router which automatically suppresses these problems. In the future, this FPGA will also be used in the information, transport and healthcare fields, and the size of the market is expected to reach 1 trillion yen in the year 2020. This work has great social significance due to its contribution to improving the reliability of social infrastructure.
For above reasons, Dr. Ibe, Mr. Toba, and Mr. Shinbo have been awarded the 15th Yamazaki-Teiichi Prize in the Semiconductor and Semiconductor Devices field.
SRAM: Static Random Access Memory, FPGA: Field Programmable Gate Array

Background of research and development

Terrestrial neutrons, which are produced by nuclear reactions between high-energy cosmic protons and nuclei such as nitrogen and oxygen nuclei in the atmosphere as shown in Fig.1 (a), have drastically been causing soft-errors (data flip in memory) in SRAMs (static random access memories) since the late 1990s. A number of SRAMs have been implemented in electronic systems such as networks or automotives and their soft-errors have caused serious failures, as illustrated in Fig. 1(b)
To clarify the mechanism of soft-errors and establish a cost-effective protection architecture against failures in electronic systems, measurement and quantification technologies are of primary importance.

Fig.Concept of the origin of terrestrial neutrons and resultant failure in electronic systems
Fig. 1 Concept of the origin of terrestrial neutrons and resultant failure in electronic systems


The winners of the prize have established a quasi-monoenergetic neutron beam method, which utilizes high-energy protons as precursors of high-energy neutrons. The method has been accepted as the international standard in 2006.
Prior to the achievement of a minimum feature size of 180 nm in semiconductor generation, terrestrial neutron-induced soft-errors were regarded to take place only in one single bit (one memory cell). However, after the semiconductor technology nose-dived into the 130 nm range, broad and multiple mode soft-errors emerged; typical examples are illustrated in Fig. 2. In the mode, it is found for the first place that in using the quasi-monoenergetic neutron method, only two adjacent bits fail along with a single word line but two or more bits fail along with a bit line. The winners scrutinized the new error patters and clarified their physical mechanism through the development of systematic and accurate simulators incorporating the first principle nuclear reaction and movement of charged particles modeled in a semiconductor memory array.
Based on the physical mechanism and specific error patters, the winners developed complete countermeasures against terrestrial neutron soft-errors in SRAMs and verified the efficiency of the methods in 2006.

Fig. 2 Cross section of FeRAM. The protective film blocks the ingress of hydrogen from outside.
Fig. 2 Drastic changes in terrestrial neutron-induced soft-error patters from
(a) 180 nm generation to (b) 130 nm generation

Furthermore, during 2009 and beyond, when non-reproducible failures occurred in network systems and their causes were unknown, establishment of the countermeasures was regarded as the top-priority issue. In 2011, the winners developed a new technique to identify vulnerable parts in circuit boards and verified that failures in network systems are mostly caused by terrestrial neutrons.
The use of FPGAs (field programmable gate arrays), in which any logic circuit can be implemented accustomed to the application by keeping logic circuit information in SRAM-like cells, has been increasing since the 2000s and they are being used as major components in network systems. However, they are known to be vulnerable to terrestrial neutron-induced soft-errors.
The winners have developed a new architecture by which the sources of failures due to terrestrial neutrons in electronic systems can be identified during operation, and they found that FPGAs are increasingly becoming vulnerable. Finally, a prompt protection architecture was developed as a high-speed, completely self-diagnosing, and resume technology, as illustrated in Fig.3. In 2012, its perfect efficiency was verified in actual network systems in Japan.

Meaning of the achievements

Since the IoT (Internet of Things) era, where trillions of sensors are inter-connected through networks, has been in the spotlight recently, ultra-high-speed functions and real time responses have been in strong demand in major ICT fields such as big-data and artificial intelligence.
FPGAs, therefore, will be prominently applied to a broad market on a 10-million-dollar scale, thanks to their features superior to CPUs such as acceleration technique. This is supported by the fact that large processor vendors are taking a step towards using FPGAs as key components in electronic systems for dependability. Consequently, the utilization of the protection architecture will continuously increase.

Fig. 4  FeRAM market
Fig. 3 Concept and features of the prompt protection architecture